Everything about Placement Eda totally explained
Placement is an essential step in
electronic design automation - the portion of the physical design flow that assigns exact locations for various circuit
components within the chip’s core area. An inferior placement assignment won't only affect the
chip's performance but might also make it nonmanufacturable by producing excessive wirelength, which
is beyond available
routing resources. Consequently, a placer must perform the assignment while optimizing
a number of objectives to ensure that a circuit meets its performance demands. Typical placement
objectives include
- Total wirelength: Minimizing the total wirelength, or the sum of the length of all the wires in the design, is the primary objective of most existing placers. This not only helps minimize chip size, and hence cost, but also minimizes power and delay, which are proportional to the wirelength and wirelength squared, respectively.
- Timing: The clock cycle of a chip is determined by the delay of its longest path, usually referred to as the critical path. Given a performance specification, a placer must ensure that no path exists with delay exceeding the maximum specified delay.
- Congestion: While it's necessary to minimize the total wirelength to meet the total routing resources, it's also necessary to meet the routing resources within various local regions of the chip’s core area. A congested region might lead to excessive routing detours, or make it impossible to complete all routes.
- Power: Power minimization typically involves distributing the locations of cell components so as to reduce the overall power consumption, alleviate hot spots, and smooth temperature gradients.
- A secondary objective is placement runtime minimization.
Placement within the EDA design flow
A placer takes a given synthesized
circuit
netlist together with a technology library and produces a valid placement layout. The layout
is optimized according to the aforementioned objectives and ready for cell resizing and buffering — a step
essential for
timing and
signal integrity satisfaction.
Clock-tree synthesis and
routing follow, completing the physical design process.
In many cases, parts of, or the entire, physical design flow are iterated a number
of times until
design closure is achieved.
In the case of
application-specific integrated circuits, or ASICs, the chip’s core layout area comprises a
number of fixed height rows, with either some or no space between them. Each row consists of a number
of sites which can be occupied by the circuit components. A free site is a site that isn't occupied by any component. Circuit components are either standard cells, macro blocks, or I/O pads. Standard cells have a
fixed height equal to a row’s height, but have variable widths. The width of a cell is an integral number of
sites. On the other hand, blocks are typically larger than cells and have variable heights that can stretch a
multiple number of rows. Some blocks can have preassigned
locations — say from a previous floorplanning process — which limit the placer’s task to assigning locations
for just the cells. In this case, the blocks are typically referred to by fixed blocks. Alternatively, some or
all of the blocks may not have preassigned locations. In this case, they've to be placed with the cells in
what is commonly referred to as mixed-mode placement.
In addition to ASICs, placement retains its prime importance in gate array structures such as
field-programmable gate arrays (FPGAs). In FPGAs, placement maps the circuit’s subcircuits into programmable FPGA logic blocks in a manner that guarantees the completion of the subsequent stage of routing.
Basic techniques
Analytical techniques approximate the wirelength objective using quadratic or nonlinearformulations.
The advent of min-cut partitioners paved the way to the introduction of min-cut placers.
Another thread of placement techniques started with the proposal of simulated annealing as a general combinatorial optimization technique.Further Information
Get more info on 'Placement Eda'.
|
External Link Exchanges
Do you know how hard it is to get a link from a large encyclopaedia? Well we're different and will prove it. To get a link from us just add the following HTML to your site on a relevant page:
<a href="http://placement__eda.totallyexplained.com">Placement (EDA) Totally Explained</a>
Then simply click through this link from your web page. Our crawlers will verify your link, extract the title of your web page and instantly add a link back to it. If you like you can remove the words Totally Explained and embed the link in article text.
As long as your link remains in place, we'll keep our link to you right here. Please play fair - our crawlers are watching. Your site must be closely related to this one's topic. Any kind of spamming, dubious practises or removing the link will result in your link from us being dropped and, potentially, your whole site being banned. |
